Publications


Conference Papers

  1. McKay Mower, Luke Majors, and Tsung-Wei Huang, "Taskflow-San: Sanitizing Erroneous Control Flow in Taskflow Programs," IEEE Workshop on Extreme Scale Programming Models and Middleware (ESPM2), St. Louis, Missouri, 2021
  2. Tsung-Wei Huang, "TFProf: Profiling Large Taskflow Programs with Modern D3 and C++," IEEE International Workshop on Programming and Performance Visualization Tools (ProTools), St. Louis, Missouri, 2021
  3. Yasin Zamani and Tsung-Wei Huang, "A High-Performance Heterogeneous Critical Path Analysis Framework," IEEE High-Performance Extreme Computing Conference (HPEC), MA, 2021.
  4. Cheng-Hsiang Chiu, Dian-Lun Lin, and Tsung-Wei Huang, "An Experimental Study of SYCL Task Graph Parallelism for Large-Scale Machine Learning Workloads," International Workshop of Asynchronous Many-Task systems for Exascale (AMTE), Portugal, 2021.
  5. Dian-Lun Lin and Tsung-Wei Huang, "Efficient GPU Computation using Task Graph Parallelism," European Conference on Parallel and Distributed Computing (Euro-Par), Portugal, 2021.
  6. Guannan Guo, Tsung-Wei Huang, Yibo Lin, and Martin Wong, "GPU-accelerated Path-based Timing Analysis," IEEE/ACM Design Automation Conference (DAC), CA, 2021.
  7. Zizheng Guo, Tsung-Wei Huang, and Yibo Lin, "A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs," IEEE/ACM Design Automation Conference (DAC), CA, 2021.
  8. Kuan-Ming Lai, Tsung-Wei Huang, Pei-Yu Lee, and Tsung-Yi Ho, "ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing Analysis," IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Japan, 2021.
  9. Chun-Xun Lin, Tsung-Wei Huang, and Martin Wong, "An Efficient Work-Stealing Scheduler for Task Dependency Graph," IEEE International Conference on Parallel and Distributed Systems (ICPADS), Hong Kong, 2020.
  10. Dian-Lun Lin and Tsung-Wei Huang, "A Novel Inference Algorithm for Large Sparse Neural Network using Task Graph Parallelism," IEEE High-performance and Extreme Computing Conference (HPEC), MA, 2020.
  11. Zizheng Guo, Tsung-Wei Huang, and Yibo Lin, "GPU-accelerated Static Timing Analysis," IEEE/ACM International Conference on Computer-aided Design (ICCAD), CA, 2020.
  12. Tsung-Wei Huang, "A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD," IEEE/ACM International Conference on Computer-aided Design (ICCAD), CA, 2020.
  13. I.-C. Lin, U. Schlichtmann, Tsung-Wei Huang, and M. P.-H. Lin, "Overview of 2020 CAD Contest at ICCAD," IEEE/ACM International Conference on Computer-aided Design (ICCAD), CA, 2020.
  14. Guannan Guo, Tsung-Wei Huang, Chun-Xun Lin, and Martin Wong, "An Efficient Critical Path Generation Algorithm Considering Extensive Path Constraints," ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2020.
  15. Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, and Martin Wong, "A Modern C++ Parallel Task Programming Library," ACM Multimedia Conference (MM), pp. 2285-2287, Nice, France, 2019.
  16. Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, and Martin Wong, "An Efficient and Composable Parallel Task Programming Library," IEEE High-performance and Extreme Computing Conference (HPEC), Waltham, MA, 2019.
  17. Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, and Martin Wong, "Cpp-Taskflow: Fast Task-based Parallel Programming using Modern C++," IEEE International Parallel and Distributed Processing Symposium (IPDPS), pp. 974-983, Rio de Janeiro, Brazil, 2019.
  18. Kuan-Ming Lai, Tsung-Wei Huang, and Tsung-Yi Ho, "A General Cache Framework for Efficient Generation of Timing Critical Paths," ACM/IEEE Design Automation Conference (DAC), pp. 108:1-108:6, Las Vegas, NV, 2019.
  19. Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, and Martin Wong, "Essential Building Blocks for Creating an Open-source EDA Project," ACM/IEEE Design Automation Conference (DAC), pp. 78:1-78:4, Las Vegas, NV, 2019.
  20. Tsung-Wei Huang, Chun-Xun Lin, and Martin Wong, "Distributed Timing Analysis at Scale," ACM/IEEE Design Automation Conference (DAC), pp. 1-2, Las Vegas, NV, 2019.
  21. Tsung-Wei Huang, Chun-Xun Lin, Guannan Guo, and Martin Wong, "A General-purpose Distributed Programming System using Data-parallel Streams," ACM Multimedia Conference (MM), pp. 1360-1363, Seoul, Korea, 2018.
  22. Chun-Xun Lin, Tsung-Wei Huang, Guannan Guo, and Martin Wong, "MtDetector: A High-performance Marine Traffic Detector at Stream Scale," ACM International Conference on Distributed and Event-based Systems (DEBS), pp. 205-208, Hamilton, New Zealand, 2018.
  23. Chun-Xun Lin, Tsung-Wei Huang, Ting Yu, and Martin Wong, "A Distributed Power Grid Analysis Framework from Sequential Stream Graph," ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 183-188, Chicago, IL, 2018.
  24. Chun-Xun Lin, Tsung-Wei Huang, and Martin Wong, "Routing at Compile Time," IEEE International Symposium on Quality Electronic Design (ISQED), pp. 169-175, Santa Clara, CA, 2018
  25. Tsung-Wei Huang, Chun-Xun Lin, and Martin Wong, "DtCraft: A Distributed Execution Engine for Compute-intensive Applications," IEEE/ACM International Conference on Computer-aided Design (ICCAD), pp. 757-765, Irvine, CA, 2017.
  26. T.-Y. Lai, Tsung-Wei Huang, and Martin Wong, "Libabs: An Effective and Accurate Macro-modeling Algorithm for Large Hierarchical Designs," IEEE/ACM Design Automation Conference (DAC), pp. 1-6, Austin, TX, 2017.
  27. Tsung-Wei Huang, Martin Wong, D. Sinha, K. Kalafala, and N. Venkateswaran, "A Distributed Timing Analysis Framework for Large Designs," IEEE/ACM Design Automation Conference (DAC), pp. 116:1-116:6, Austin, TX, 2016.
  28. Tsung-Wei Huang and Martin Wong, "OpenTimer: A High-Performance Timing Analysis Tool," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 895-902, Austin, TX, 2015.
  29. Tsung-Wei Huang and Martin Wong, "On Fast Timing Closure: Speeding Up Incremental Path-Based Timing Analysis with MapReduce," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP), CA, 2015.
  30. Tsung-Wei Huang and Martin Wong, "Accelerated Path-Based Timing Analysis with MapReduce," ACM International Symposium on Physical Design (ISPD) (slide), pp. 103-110, Monterey, CA, 2015.
  31. Tsung-Wei Huang, P.-C. Wu, and Martin Wong, "Fast Path-Based Timing Analysis for CPPR," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 596-599, San Jose, CA, 2014.
  32. Tsung-Wei Huang, P.-C. Wu, and Martin Wong, "UI-Timer: An Ultra-Fast Clock Network Pessimism Removal Algorithm," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 758-765, San Jose, CA, 2014.
  33. Tsung-Wei Huang, P.-C. Wu, and Martin Wong, "UI-Route: An Ultra-Fast Incremental Maze Routing Algorithm," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP) (slide), San Francisco, CA, 2014.
  34. S.-H. Yeh, J.-W. Chang, Tsung-Wei Huang, and Tsung-Yi Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 353-360, San Jose, CA, 2012.
  35. Tsung-Wei Huang, J.-W. Chang, and Tsung-Yi Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," ACM International Symposium on Physical Design (ISPD), pp. 49-56, Napa, CA, 2012
  36. Jia-Wei Chang, Tsung-Wei Huang, and Tsung-Yi Ho, "An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 67-72, Sydney, Australia, 2012
  37. Tsung-Wei Huang, Tsung-Yi Ho, and K. Chakrabarty, "Reliability-Oriented Broadcast Electrode-Addressing for Pin-Constrained Digital Microfluidic Biochips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 448-455, San Jose, CA, 2011
  38. Tsung-Wei Huang, Yan-You Lin, Jia-Wei Chang, and Tsung-Yi Ho, "Chip-Level Design and Optimization for Digital Microfluidic Biochips," Proceeding of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2011
  39. Tsung-Wei Huang and Tsung-Yi Ho, "Recent Research and Emerging Challenges in the Designs and Optimizations for Digital Microfluidic Biochips," Proceeding of IEEE System on Chip Conference (SOCC), pp. 12-17, Taipei, Taiwan, 2011
  40. P.-H. Yuh, C.-Y Lin, Tsung-Wei Huang, Tsung-Yi Ho, C.-L. Yang, and Yao-Wen Chang, "A SAT-Based Routing Algorithm for Cross-Referencing Biochips," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP) (slide), San Diego, CA, 2011
  41. Tsung-Wei Huang, H.-Y. Su, and Tsung-Yi Ho, "Progressive Network-Flow Based Power-Aware Broadcast Addressing for Pin-Constrained Digital Microfluidic Biochips," ACM/IEEE Design Automation Conference (DAC) (slide), pp. 741-746, San Diego, CA, 2011
  42. Tsung-Wei Huang, S.-Y. Yeh, and Tsung-Yi Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast Electrode-Addressing EWOD Chips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 425-431, San Jose, CA, 2010
  43. Tsung-Wei Huang and Tsung-Yi Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," ACM International Symposium on Physical Design (ISPD) (slide), pp. 201-208, San Francisco, CA, 2010
  44. Tsung-Wei Huang, C.-H. Lin, and Tsung-Yi Ho, "A Contamination Aware Droplet Routing Algorithm for Digital Microfluidic Biochips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 151-156, San Jose, CA, 2009
  45. Tsung-Wei Huang and Tsung-Yi Ho, "A Fast Routability- and Performance-Driven Droplet Routing Algorithm for Digital Microfluidic Biochips," IEEE International Conference on Computer Design (ICCD) (slide), pp. 445-450, Lake Tahoe, CA, 2009

Journal Papers

  1. Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, and Yibo Lin, "A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD), accepted, 2021
  2. Jia-Ruei Yu, Chun-Hsien Chen, Tsung-Wei Huang, Jang-Jih Lu, Chia-Ru Chung, Ting-Wei Lin, Min-Hsien Wu, Yi-Ju Tseng, Hsin-Yao Wang, "Energy Efficiency of Inference Algorithms for Medical Datasets: A Green AI study," Journal of Medical Internet Research (JMIR), accepted, 2021
  3. Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin, and Yibo Lin, "Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System," IEEE Transactions on Parallel and Distributed Systems (TPDS), accepted, 2021
  4. Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, and Chun-Xun Lin, "Taskflow: A General-purpose Parallel and Heterogeneous Task Programming Systesm," IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD), accepted, 2021
  5. Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, and Martin Wong, "Cpp-Taskflow: A General-purpose Parallel Task Programming System at Scale," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 8, pp. 1687-1700, Aug. 2021
  6. Tsung-Wei Huang, Guannan Guo, Chun-Xun Lin, and Martin Wong, "OpenTimer v2: A New Parallel Incremental Timing Analysis Engine," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 4, pp. 776-786, April 2021
  7. Tsung-Wei Huang, Chun-Xun Lin, and Martin Wong, "OpenTimer v2: A Parallel Incremental Timing Analysis Engine," IEEE Design and Test (DAT), vol. 38, no. 2, pp. 62-68, April 2021
  8. Tsung-Wei Huang, Chun-Xun Lin, and Martin Wong, "DtCraft: A High-performance Distributed Execution Engine at Scale," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 6, pp. 1070-1083, June 2019
  9. Tsung-Wei Huang and Martin Wong, "UI-Timer 1.0: An Ultra-Fast Path-Based Timing Analysis Algorithm for CPPR," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 11, pp. 1862-1875, Nov. 2016
  10. S.-H. Yeh, J.-W. Chang, Tsung-Wei Huang, S.-T. Yu, and Tsung-Yi Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 9, pp. 1302-1315. Sept. 2014
  11. J.-W. Chang, S.-H. Yeh, Tsung-Wei Huang, and Tsung-Yi Ho, "An ILP-based Routing Algorithm for Pin-Constrained EWOD Chips with Obstacle Avoidance," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 11, pp. 1655-1667, Nov. 2013
  12. Y.-H. Chen, C.-L. Hsu, L.-C. Tsai, Tsung-Wei Huang, and Tsung-Yi Ho, "A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3D Deferred Decision Making Technique," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 8, pp. 1151-1162, Aug. 2013
  13. J.-W. Chang, S.-H. Yeh, Tsung-Wei Huang, and Tsung-Yi Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 2, pp. 216-227, Feb. 2013
  14. Tsung-Wei Huang, S.-Y. Yeh, and Tsung-Yi Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, no. 12, pp. 1786-1799, Dec. 2011
  15. Tsung-Wei Huang and Tsung-Yi Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, no. 2, pp. 215-228, Feb. 2011
  16. Tsung-Wei Huang, C.-H. Lin, and Tsung-Yi Ho, "A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 11, pp. 1682-1695, Nov. 2010

Patents

  1. Tsung-Wei Huang, K. Kalafala, D. Sinha, and N. Venkateswaran, "Distributed Timing Analysis of a Partitioned Integrated Circuit Design," US20170242945A1, 08/24/2017
  2. Tsung-Wei Huang, K. Kalafala, V. B. Rao, D. Sinha, and N. Venkateswaran, "Incremental Common Path Pessimism Analysis," US9836572B2, 12/05/2017

Thesis

  1. Tsung-Wei Huang, "Distributed Timing Analysis," PhD Dissertation, University of Illinois at Urbana-Champaign (UIUC), Dec 2017
  2. T.-W Huang, "Routing for Digital Microfluidic Biochips: From Fluidic-Level toward Chip-Level," Master Thesis, National Cheng-Kung University, Taiwan, July 2011