Tsung-Wei Huang

Research Assistant Professor, CSL & ECE
University of Illinois at Urbana-Champaign, IL, USA
Office: 402 Coordinated Science Lab MC 228
BS/MS (NCKU), PhD (UIUC)          

Research Presentation Teaching People Awards Publication Service Thank-you

Recent News

More news (click to expand)

  • 2018/09/30: Cpp-Taskflow won the Best Poster Award in 2018 Official C++ Conference

Research

My research group works on large-scale and complex software systems with a specific focus on parallel and distributed computing, programming models, electronic design automation, machine learning systems, etc.

Most of our research projects are open-source under permissive licenses.

Cpp-Taskflow: Fast Task-based Parallel Programming using Modern C++

Cpp-Taskflow introduces a new parallel task programming model to help C++ developers quickly write parallel programs and implement efficient parallel decomposition strategies.

DtCraft: A Distributed Programming System using Data-parallel Streams

DtCraft introduces a new C++ stream graph programming model to help developers streamline the building of high-performance distributed applications on a machine cluster.

OpenTimer: A High-performance Timing Analysis Tool for VLSI Systems

OpenTimer develops an efficient parallel incremental timing to help circuit designers quckly analyze the timing of complex designs that incorporate billions of transistors and more.


Presentation

Here is a list of presentation slides related to our research. You are free to use it and distribute it to any places you want.


Teaching

The following courses are given at UIUC. I am currently teaching ECE462 at the Spring Semester.


People


Awards

More awards (click to expand)

  • Outstanding Student Scholarship, Garmin Corporation, Taiwan, 2010
  • Outstanding Graduate Fellowship, National Cheng Kung University, Taiwan, 2010 (CS Graduate Fellowship)
  • EDA Scholarship, SpringSoft Education Foundation, 2009 and 2010
  • Outstanding Engineering Student Fellowship, Chinese Institute of Engineers, Taiwan, 2010 (CIE Fellowship 2010)
  • Third Place, National Collegiate Cell-Based IC Design Contest, Ministry of Education, Taiwan, 2010
  • First Place, National Collegiate Nano Device CAD Contest, Nano Device Laboratories, Taiwan, 2009
  • Third Place, National Collegiate Programming Contest, Ministry of Education, Taiwan, 2009
  • Travel Grant Award, Foundation for the Advancement of Outstanding Scholarship, Taiwan, 2009
  • Second Place, National Collegiate IC/CAD Contest, Ministry of Education, Taiwan, 2008 (CAD Contest 2007)
  • Presidential Award (top 2% students), Department of Computer Science, National Cheng Kung University, Taiwan 2007

Publication

Conference Papers

  1. T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, "Cpp-Taskflow: Fast Task-based Parallel Programming using Modern C++," IEEE International Parallel and Distributed Processing Symposium (IPDPS), Rio de Janeiro, Brazil, 2019.
  2. K.-M. Lai, T.-W. Huang, and T.-Y. Ho, "A General Cache Framework for Efficient Generation of Timing Critical Paths," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.
  3. T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, "INVITED: Essential Building Blocks for Creating an Open-source EDA Project," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.
  4. T.-W. Huang, C.-X. Lin, and Martin D. F. Wong, "Late Breaking Results: Distributed Timing Analysis at Scale," ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.
  5. T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, "A General-purpose Distributed Programming System using Data-parallel Streams," ACM Multimedia Conference (MM), Seoul, Korea, 2018.
  6. C.-X. Lin, T.-W. Huang, G. Guo, and Martin D. F. Wong, "MtDetector: A High-performance Marine Traffic Detector at Stream Scale," ACM International Conference on Distributed and Event-based Systems (DEBS), Hamilton, New Zealand, 2018.
  7. C.-X. Lin, T.-W. Huang, Ting Yu, and Martin D. F. Wong, "A Distributed Power Grid Analysis Framework from Sequential Stream Graph," ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, IL, 2018.
  8. C.-X. Lin, T.-W. Huang, and Martin D. F. Wong, "Routing at Compile Time," IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, 2018
  9. T.-W. Huang, C.-X. Lin, and Martin D. F. Wong, "DtCraft: A Distributed Execution Engine for Compute-intensive Applications," IEEE/ACM International Conference on Computer-aided Design (ICCAD), Irvine, CA, 2017.
  10. T.-Y. Lai, T.-W. Huang, and Martin D. F. Wong, "Libabs: An Effective and Accurate Macro-modeling Algorithm for Large Hierarchical Designs," IEEE/ACM Design Automation Conference (DAC), Austin, TX, 2017.
  11. T.-W. Huang, Martin D. F. Wong, D. Sinha, K. Kalafala, and N. Venkateswaran, "A Distributed Timing Analysis Framework for Large Designs," IEEE/ACM Design Automation Conference (DAC), Austin, TX, 2016.
  12. T.-W. Huang and Martin D. F. Wong, "OpenTimer: A High-Performance Timing Analysis Tool," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 895-902, Austin, TX, 2015.
  13. T.-W. Huang and Martin D. F. Wong, "On Fast Timing Closure: Speeding Up Incremental Path-Based Timing Analysis with MapReduce," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP), CA, 2015.
  14. T.-W. Huang and Martin D. F. Wong, "Accelerated Path-Based Timing Analysis with MapReduce," ACM International Symposium on Physical Design (ISPD) (slide), pp. 103-110, Monterey, CA, 2015.
  15. T.-W. Huang, P.-C. Wu, and Martin D. F. Wong, "Fast Path-Based Timing Analysis for CPPR," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 596-599, San Jose, CA, 2014 (invited paper).
  16. T.-W. Huang, P.-C. Wu, and Martin D. F. Wong, "UI-Timer: An Ultra-Fast Clock Network Pessimism Removal Algorithm," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 758-765, San Jose, CA, 2014.
  17. T.-W. Huang, P.-C. Wu, and Martin D. F. Wong, "UI-Route: An Ultra-Fast Incremental Maze Routing Algorithm," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP) (slide), San Francisco, CA, 2014.
  18. S.-H. Yeh, J.-W. Chang, T.-W. Huang, and T.-Y. Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 353-360, San Jose, CA, 2012.
  19. T.-W. Huang, J.-W. Chang, and T.-Y. Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," ACM International Symposium on Physical Design (ISPD), pp. 49-56, Napa, CA, 2012
  20. J.-W. Chang, T.-W. Huang, and T.-Y. Ho, "An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips," IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 67-72, Sydney, Australia, 2012
  21. T.-W. Huang, T.-Y. Ho, and K. Chakrabarty, "Reliability-Oriented Broadcast Electrode-Addressing for Pin-Constrained Digital Microfluidic Biochips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 448-455, San Jose, CA, 2011
  22. T.-W. Huang, Y.-Y. Lin, J.-W. Chang, and T.-Y. Ho, "Chip-Level Design and Optimization for Digital Microfluidic Biochips," Proceeding of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2011
  23. T.-W. Huang and T.-Y. Ho, "Recent Research and Emerging Challenges in the Designs and Optimizations for Digital Microfluidic Biochips," Proceeding of IEEE System on Chip Conference (SOCC), pp. 12-17, Taipei, Taiwan, 2011
  24. P.-H. Yuh, C. C.-Y. Lin, T.-W. Huang, T.-Y. Ho, C.-L. Yang, and Y.-W. Chang, "A SAT-Based Routing Algorithm for Cross-Referencing Biochips," IEEE/ACM International Workshop on System Level Interconnect Prediction (SLIP) (slide), San Diego, CA, 2011
  25. T.-W. Huang, H.-Y. Su, and T.-Y. Ho, "Progressive Network-Flow Based Power-Aware Broadcast Addressing for Pin-Constrained Digital Microfluidic Biochips," ACM/IEEE Design Automation Conference (DAC) (slide), pp. 741-746, San Diego, CA, 2011
  26. T.-W. Huang, S.-Y. Yeh, and T.-Y. Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast Electrode-Addressing EWOD Chips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 425-431, San Jose, CA, 2010
  27. T.-W. Huang and T.-Y. Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," ACM International Symposium on Physical Design (ISPD) (slide), pp. 201-208, San Francisco, CA, 2010
  28. T.-W. Huang, C.-H. Lin, and T.-Y. Ho, "A Contamination Aware Droplet Routing Algorithm for Digital Microfluidic Biochips," IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (slide), pp. 151-156, San Jose, CA, 2009
  29. T.-W. Huang and T.-Y. Ho, "A Fast Routability- and Performance-Driven Droplet Routing Algorithm for Digital Microfluidic Biochips," IEEE International Conference on Computer Design (ICCD) (slide), pp. 445-450, Lake Tahoe, CA, 2009

Journal Papers

  1. T.-W. Huang, C.-X. Lin, and Martin D. F. Wong, "DtCraft: A High-performance Distributed Execution Engine at Scale," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), to appear in 2019.
  2. T.-W. Huang and Martin D. F. Wong, "UI-Timer 1.0: An Ultra-Fast Path-Based Timing Analysis Algorithm for CPPR," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 11, pp. 1862-1875. Nov. 2016
  3. S.-H. Yeh, J.-W. Chang, T.-W. Huang, S.-T. Yu, and T.-Y. Ho, "Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 9, pp. 1302-1315. Sept. 2014
  4. J.-W. Chang, S.-H. Yeh, T.-W. Huang, and T.-Y. Ho, "An ILP-based Routing Algorithm for Pin-Constrained EWOD Chips with Obstacle Avoidance," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 11, pp. 1655-1667, Nov. 2013
  5. Y.-H. Chen, C.-L. Hsu, L.-C. Tsai, T.-W. Huang, and T.-Y. Ho, "A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3D Deferred Decision Making Technique," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 8, pp. 1151-1162, Aug. 2013
  6. J.-W. Chang, S.-H. Yeh, T.-W. Huang, and T.-Y. Ho, "Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 2, pp. 216-227, Feb. 2013
  7. T.-W. Huang, S.-Y. Yeh, and T.-Y. Ho, "A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, no. 12, pp. 1786-1799, Dec. 2011
  8. T.-W. Huang and T.-Y. Ho, "A Two-Stage ILP-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, no. 2, pp. 215-228, Feb. 2011
  9. T.-W. Huang, C.-H. Lin, and T.-Y. Ho, "A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 11, pp. 1682-1695, Nov. 2010

Patents

  1. T.-W. Huang, K. Kalafala, D. Sinha, and N. Venkateswaran, "Distributed Timing Analysis of a Partitioned Integrated Circuit Design," US20170242945A1, 08/24/2017
  2. T.-W. Huang, K. Kalafala, V. B. Rao, D. Sinha, and N. Venkateswaran, "Incremental Common Path Pessimism Analysis," US9836572B2, 12/05/2017

Service

Conference Reviewer

Journal Reviewer

Organizer

Program Committee


Acknowledgment

I could not come this far without great people around who have supported, motivated, and inspired me to continue growing. I am also grateful for many organizations to support my research.